Zilog eZ80

Architecture and classificationInstruction setZ80^[a]HistoryPredecessorZilog Z80

The Zilog eZ80 is an 8-bit microprocessor designed by Zilog as an updated version of the company's first product, the highly-successful Zilog Z80. The eZ80 is binary compatible with the Z80, but operating almost three times faster at the same clock frequency.

Zilog eZ80 registers in ADL mode

23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers 0 0 0 0 0 0 0 0 Accumulator (A) Flags (F) AF BCU B C BC DEU D E DE HLU H L HL Alternate (shadow) registers 0 0 0 0 0 0 0 0 Accumulator' (A') Flags' (F') AF' BCU' B' C' BC' DEU' D' E' DE' HLU' H' L' HL' Index registers IXU IXH IXL IX IYU IYH IYL IY Stack Pointer SPL Other registers Interrupt vector (base) 0 0 0 0 0 0 0 0 I   Memory base MBASE   Refresh counter R Program counter Program Counter PC Status flags   S Z - H - P/V N C Flags   ADL EF1 EF2 MADL Bit flags

The eZ80 has a three-stage pipeline: fetch, decode, and execute. When an instruction changes the program counter, it flushes the instructions that the CPU is currently processing. Available at up to 50 MHz (2004), the performance is comparable to a Z80 clocked at 150 MHz if fast memory is used (i.e. no wait states for opcode fetches, for data, or for I/O) or even higher in some applications (a 16-bit addition is 11 times as fast as in the original). The original Z80-compatible 16-bit register configuration is supported. The eZ80 also supports direct continuous addressing of 16 MB of memory without a memory management unit, by extending most registers (HL, BC, DE, IX, IY, SP, and PC) from 16 to 24 bits. In order to do so, the CPU has a full 24-bit address mode called ADL mode. In ADL mode, all Z80 16-bit registers are extended to 24 bits with additional upper 8-bit registers. For example, the HL register pair is extended with an uppermost register called HLU. The resulting 24-bit multi-byte register is collectively accessed by its old name, HL. The upper registers cannot be accessed individually.^[2]

The processor has a 24-bit ALU arithmetic logic unit and overlapped processing of several instructions (the three-stage pipeline) which are the two primary reasons for its speed. Unlike the older Z280 and Z380 it does not have (or need) a cache memory. Instead, it is intended to work with fast SRAM directly as main memory (as this had become much cheaper). Nor does it have the multiplexed bus of the Z280, making it as easy to work with (interface to) as the original Z80 and Z180, and equally predictable when it comes to exact execution times.

The chip has a memory interface that is similar to the original Z80, including the bus request/acknowledge pins, and adds four integrated chip selects. Versions are available with on-chip flash memory and on-chip zero wait-state SRAM (up to 256 KB flash memory and 16 KB SRAM) but there are also external buses on all models.

The eZ80 family includes several variants offering different levels of integration. These single-chip computers retain an external address and data bus so they can function as general-purpose microprocessors despite their focus on specific applications.

The eZ80Acclaim! line integrates up to 128 KB of flash memory and 8 KB of SRAM, operating at speeds up to 20 MHz.^[3][4]

The eZ80AcclaimPlus! adds an Ethernet controller and TCP/IP stack to the eZ80Acclaim! features, reaching speeds of up to 50 MHz.^[5]

The TI-84 Plus CE graphing calculator utilizes the eZ80 in 24-bit address mode at 48 MHz.^[6] The eZ80L92 processor powers the ST Robotics robot controller, running at 50 MHz.^[7]

• Cantrell, Tom (February 2002). "eZ Embedded Web". Circuit Cellar (139). Retrieved July 15, 2009.
• Harston, J.G. (April 15, 1998). "Full eZ80 Opcode List". Retrieved July 15, 2009.